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LED7
- 七段数码管的源代码 用Quartus II 9.0 (32-Bit) 编译的七段数码管的驱动程序-thes is LED7
verilog2
- 本代码在Quartus II 9.0 (32-Bit)环境编译运行,使用SOPC_NIOSIIFPGA开发板,可作为入门级代码讲解,将50MHZ的频率改为1MHZ,并以此频率为基准计数显示在七段数码管上。(采用verilog语言)-The code in Quartus II 9.0 (32-Bit) environment to run the compiler, the use of SOPC_NIOSIIFPGA development board, entry-level code ca
quartusii9.1_handbook
- quartusii9.1_handbook用户手册吗,是最新版的altera fpga开发软件资料,altera官方资料,是学习altera fpga的必备资料,(全英文版)中文版我会尽快上传-quartusii9.1_handbook user manual you, is the latest version of the altera fpga software development information, altera official information is essentia
nios_shi
- 由nios ii实现的,用cfi flash与SDRAM共同实现的电子数字时钟,基于sopc的嵌入式代码,所用软件都是9.0版本的,包括quartus ii9.0 和nios ii9.0-Achieved by the nios ii, together with the cfi flash with SDRAM to achieve the electronic digital clock, based on sopc embedded code, the software is versio
lcd
- 用Verilog写的数码管动态显示代码,可以直接使用,在quartus ii软件9.0以上版本运行-Verilog digital control with dynamic display of written code, can be used directly in the quartus ii software, version 9.0 or above to run
mcu-fpga
- 目录 FPGA & MCU 开发板介绍 实验1 QuartusII 软件应用 实验2 Keil C51 应用 实验3 字符型LCD YM1602 的应用 实验4 带字库的中文LCD YM12864 的应用 实验5 时钟芯片DS1302 的应用 实验6 I2C 总线器件AT24C64 的应用 实验7 数字温度传感器的应用 实验8 行列式键盘 实验9 硬件电子琴的设计 实验10 AD 与DA 的使用 实验11 简易DDS 信号源设计 实验12 用模
LCD12864
- LCD12864显示 verilog hdl编译已通过 编译器 Quartus II 9.0sp2 所有文件已包含-LCD12864 Show verilog hdl compiler has compiler Quartus II 9.0sp2 through all the files included
2BCD
- 二进制转BCD码 verilog hdl Quartus II 9.0sp2 编译通过 所有的文件-Binary to BCD code verilog hdl Quartus II 9.0sp2 compile all the documents
int_div
- 基于VHDL的任意分频模块,利用Quartus II 9.0编译通过,并用示波器观察可行-VHDL-based modules of any division, the use of Quartus II 9.0 compiler, and the possible use of an oscilloscope
modelsim_testverilog
- 本代码提供了一个简单明了的利用quartus ii 9.0调用altera-modelsim的小程序,读者可以方便的利用代码来熟悉该调用操作,在极短时间内熟悉连个软件的应用。-This code provides a simple call to use quartus ii 9.0 altera-modelsim small program, readers can easily use the code to become familiar with the call operator, i
Verilog
- 基于Quartus II 9.0 (32-Bit)的Verilog语言时钟程序,五个独立按键分别可调十分秒的加减和确定,此程序通过硬件调试成功。-Based on Quartus II 9.0 (32-Bit) of the Verilog language, clock, five independent second key addition and subtraction, respectively, is adjustable and determined the success of
verilog_Common_arithmetic
- 常用逻辑运算,加法器,乘法器及除法器的verilog语言,可用modelsim或Quartus II 9.0环境-Common logic operation, adder, multiplier and divider verilog language, can be used modelsim or Quartus II 9.0 environment
dtrigger
- 常用触发器——D触发器的VERILOG语言描述,可用Quartus II 9.0 和modelsim环境实现。-Common triggers- D flip-flop of VERILOG language descr iption available Quartus II 9.0 and modelsim environment to achieve
SDRAMPNIOS-II
- 带SDRAM的nios II系统,开发环境为Quartus II 9.0 + Nios II 9.0-With the nios II SDRAM system, development environment for the Quartus II 9.0+ Nios II 9.0
dotdisplay
- 16*16点阵横向移动显示!采用QUARTUS II 9.0编译通过!-16* 16 dot matrix display lateral movement! Compiled by using QUARTUS II 9.0!
QuatersCrack
- 可以用于破解Quartus II 9.0,9.0SP2,9.1。 内部已经有说明文档。-Cracker for Quartus II 9.0,9.0SP2,9.1. Notice the readme file in it.
zheng_xian_bo
- 用Quartus II 9.0 产生正弦波的VHDL源代码。-Quartus II 9.0 VHDL source code of the sine wave.
9
- dds xinhaofashengqi quartus vhdl
QII_9.1.tar
- quartus 9 "solution" 2
(笔记)Quartus-II-9.1完全操作教程
- Quartus II 的操作指南 新手操作指南 有详细步骤和截屏(a detailed guide of Quartus II)